1. Field of the Invention
The present invention relates to static type semiconductor memory devices, and particularly to a static type semiconductor memory device with a spare column or spare row for replacing a defective memory cell row or defective memory cell column.
2. Description of the Background Art
FIG. 39 is a circuit diagram showing a structure of a memory cell of a static type random access memory (referred to as SRAM hereinafter) formed of conventional MOS transistors.
Referring to FIG. 39, a conventional memory cell includes a P channel MOS load transistor P11 and an N channel MOS driver transistor N11 connected in series between a power supply potential Vcc and a ground potential GND, and a P channel MOS load transistor P12 and an N channel MOS driver transistor N12 connected in series between power supply potential Vcc and ground potential GND. The connection node of P channel MOS load transistor P11 and N channel MOS driver transistor N11 is referred to as a storage node nm1. The connection node between P channel MOS load transistor P12 and N channel MOS driver transistor N12 is referred to as a storage node nm2.
Transistors P11 and N11 have their gates connected to storage node nm2. Transistors P12 and N12 have their gates connected to storage node nm1.
The conventional memory cell further includes an N channel MOS access transistor Tra1 provided between a bit line BL and storage node nm1, and having a gate potential controlled by a word line WL, and an N channel MOS access transistor Tra2 provided between storage node nm2 and a bit line/BL, and having a gate potential controlled by word line WL.
FIG. 40 is a diagram showing a concept of short-circuit between storage nodes of SRAM memory cells. As shown in FIG. 40, there is a case where short-circuit occurs between two storage nodes in an SRAM caused by foreign objects in the wiring or contact formation processes or by defocus in photolithography.
Such a chip that has bit error is generally subjected to a replacement process with a redundant column or row in order to be shipped as an acceptable product.
Even if this chip is passed as a product acceptable from the standpoint of memory operation by the redundancy replacement, short-circuit of the storage nodes in the case of a full CMOS SRAM cell implies that there is still a path through which a current flows from power supply potential Vcc to ground potential GND as shown in FIG. 40.
The existence of a current path in a defective memory cell becomes the cause of standby current defect in an SRAM of low power consumption. There was a problem that such a chip could not be shipped eventually as an acceptable product even if redundancy replacement is carried out.